Audio Delay Module
This project shows you how to make a unit which can produce a delay of up to 8 seconds on an input audio signal.

The circuit outputs a delayed version of an input audio signal. Depending on the amount of memory implemented and the sampling rate selected, it can store from 3 seconds to 8 seconds of audio. The audio input will be delayed by an amount selectable by the user.

This device can be used to produce a delay for many purposes. Some possible applications are:
  • Sound effects , such as echo, can be produced by adding a delay to an input signal.

  • This device can produce an effect which is sometimes referred to as "Delayed Auditory Feedback". This effect has been used to help aid those who stutter.
  • Another application of such a device would be in a "Speech Jammer". Such a device records a person speaking and then plays the audio back at a delay, which causes most people to get confused and thereby disrupts their speaking. Using the device for this purpose would require a directional microphone and directional speaker.
  • The device can also be used to delay the audio from a television broadcast. In my research, I found that some people prefer to use a separate, radio broadcast for the play by play or commentary for sporting events, and as such they wanted to be able to introduce a delay to synchronize a separate audio source to the television broadcast.
  • The circuit can be used sort of like a TiVo, but for audio only. By changing the delay setting, you can go back as far back as the buffer size permints (only 8 seconds max in this design) to catch something you missed.

  • At any rate, the device described here can be a lot of fun to play and experiment with. The input range is controllable from 0 seconds to the maximum delay by means of an analog input. This analog input can simply be driven by a potentiometer, or from an external signal. Modulating the delay input with different waveforms can produce interesting sound effects.

    Step 1: High Level Functional Description

    Audio Delay Module
    The block diagram shows how the circuit works.

    First, the input signal is amplified as needed. Next, the amplified signal is sampled and converted to a digital value by an analog to digital converter. The digital sample value is then stored in a large RAM buffer.

    The delayed waveform is created by retrieving older samples from the buffer and sending them to a digital to analog converter (DAC). The output of the DAC is low pass filtered to remove unwanted frequencies that are an inherent part of the sampling and reconstruction process.

    This process of analog to digital conversion, storage, retrieval, and digital to analog conversion runs in a continuous loop, controlled by a microprocessor. In this manner, a delayed replica of the input signal is produced at the output.

    The steps that follow provide in depth detail of how each sub circuit works. A PDF of the complete schematic is attached here, with each subcircuit highlighted a different color. The following steps explain what each sub circuit does.
    Audio Delay Module
    Audio Delay Schematic Highlighted.pdf24 KB

    Step 2: Pre Amp

    Audio Delay Module
    The pre amp circuit is used to interface the input audio to the microprocessor’s A/D converter. The
    circuit is a non inverting amplifier, with the input biased at a reference voltage (VREF) of ½ of the supply
    voltage. By biasing the non inverting input at VREF and capacitively coupling the audio, the input
    voltage at the non inverting input will be equal to the audio waveform offset by VREF, instead of
    swinging about 0 volts. This allows a waveform with positive and negative portions to be processed by
    the rest of the circuitry, which only works with positive voltages.

    Op amp U6-D is used to establish the VREF reference voltage that is ½ of the supply voltage. The
    reference voltage is set by the voltage divider created by R1 and R2, and the op amp buffers the voltage.
    The output of the op amp is VREF, and all points in the circuit labeled VREF connect to this point.

    The op amps used here are Microchip MCP6022 and MCP6024. These are essentially the same part,
    only one is a dual and the other is a quad. These parts have a full scale output that can swing from rail
    to rail (0V to 3.3V in this design).

    Resistor R5 biases the input to the op amp at VREF. The input audio is then capacitvely coupled via C1
    to the input of op amp U6-A. The result is that the voltage at the input to the op amp will be the audio
    input signal swinging above and below VREF. Biasing resistor R5 and the AC coupling capacitor also form
    a high pass filter to the input audio. The values must be chosen such that the cutoff frequency is below
    any frequencies you want to pass.

    The gain of the pre amp is given by Gain = 1 + R7/R6. Depending on the source of the input audio, the
    gain of the pre amp may need to be altered. If the input is from a source such as the line out of a
    computer, radio, DVD player, etc, then it may be of sufficient amplitude that it requires no further

    If the input is from a microphone, then amplification will be required. R7 must be chosen to configure
    the amplifier for the needed gain. The goal is to have the maximum peak to peak amplitude of the input
    audio make the best use of the input range of the microprocessors A/D converter. In this circuit, that
    means a maximum peak to peak voltage of 3.3V. If the input signal is amplified too much, the peak to
    peak value will exceed maximum input range and it will be clipped, introducing distortion. I included a
    switch (SW2) in my design so that the gain could easily be changed from 1 for higher level sources to
    about 34 for use with a microphone. The switch shorts out R7 so that the gain is reduced to 1. I have
    found that this works well with sources like the line out from a computer, radio, CD player, etc.

    R4 is used to supply power to an electret microphone if that is the input audio source. Electret type
    microphones need a power source to operate properly.

    Step 3: Low Pass (Anti aliasing) Filter

    Audio Delay Module
    Op amp U6-B is configured as a low pass filter, used as an anti-aliasing filter. An anti aliasing filter is
    often used with sampled data systems to reduce the amplitude of signals which have a frequency higher
    than one half the sample rate. Frequencies higher than one half the sample rate will appear in the
    output as lower frequency "aliases", which is undesirable.

    The filter used here is made up of a single second order Salen-Key filter. The overall cutoff frequency of
    the filter is approximately 6 kHz. R8, R9, C3, and C4 set the cutoff frequency of the filter.

    Step 4: Microprocessor

    Audio Delay Module
    Audio Delay Module
    The microprocessor (U1) used here is a Microchip 16F88, and it serves as the heart of the system. During the main program loop, the micro reads the input audio, converts it to a digital value, and stores it to the RAM chips. It then reads a sample to output back from the RAM chips, and outputs it to the DAC. The micro performs these functions, and also manages the addressing for the RAM buffer and calculates the address of the delayed sample to retrieve.

    There are also many configuration and housekeeping functions performed by the microprocessor. The general functions performed by the microprocessor as described below.

    Analog to Digital Conversion

    The microprocessor contains an internal ADC which has a resolution of 10 bits, but only 8 bits of the value are used. The two least significant bits of the value are discarded.

    There are two analog inputs read by the microprocessor during the main program loop. One is the audio input, and the second is the delay setting.

    The delay input is an analog input that determines how much delay there is between the input and output signals. 0 volts corresponds to 0% of full scale delay, and VDD corresponds to 100% of full scale delay. The value that is read is used to calculate the RAM address of the delayed sample that will be played back.

    Op amp U6-C is used to buffer the delay input voltage to the microprocessor A/D pin. The analog value for the delay input can be generated by a potentiometer which is used to set the voltage at this pin, providing a delay from 0 seconds to full scale. This allows a fixed delay amount to be set easily. It can also be useful to use an external signal to control the delay. All kinds of strange sound effects can be produced by driving the delay setting input with different waveforms. For that reason, my design also includes a connector to allow an external source to be used to drive the delay setting input. The schematic shows the delay setting potentiometer R24 with the wiper connected to the input of U6-C via a 10k resistor, R3. With the R3 in place, the external signal which is input via the connector can still drive the op amp input, even with the potentiometer connected. C24 helps to low pass filter the delay input signal.

    SPI Bus Master

    The micro communicates with the RAM and DAC chips using the SPI communications interface. The micro is configured as the master, and the RAM and DAC chips are slave devices. All the SPI communications are therefore initiated and controlled by the microprocessor.

    Determine Full Scale Delay Setting

    The full scale delay range is configurable by setting the 3 digital inputs either high or low. This allows the user to select a full scale range that is smaller than the total RAM buffer size. R10, R11, and R12 are used to pull up the digital inputs. Switches S1-A, S1-B, and S1-C are a quad DIP switch. When any of the switches are closed, the corresponding digital input is pulled low.

    The table included here shows the different full scale delay values possible based on the switch setting, sample rate,and RAM capacity,

    Determine RAM Configuration

    The microprocessor also determines whether the system is configured for one or two RAM chips. Resistor R13 needs to be used if two chips are to be used. When the circuit is first powered up, the microprocessor reads the line as an input. If the line is high, the software is configured for two RAM chips, and the addressing used internally is set up for that. The line will be used for the chip select signal for the second RAM chip in that configuration. If only one chip is to be used, pull the line low using R14. Only one of these resistors (either R13 or R14) should be populated at one time, depending on how many RAM chips are used. These lines need to be configured by tying them high or low via a large value resistor (10k was used here), otherwise the line to the microprocessor may be damaged.


    The micro can operate with a maximum of 20MHz for the clock frequency. An external 20MHz oscillator (X1) is used here. All the circuitry here is run from 3.3V, but the oscillator is a 5 Volt part. Resistor R16 is put in series between the oscillator output and the microprocessor clock input, to limit current so that it can drive the 3.3V powered microprocessor without issue. Inside the microprocessor, the voltage of the clock pulses is clamped to 3.3V, and so the microprocessor input is not damaged.

    Capacitor C6 is a bypass capacitor for the oscillator.

    LED Indicator

    LED1 is used to blink status or error codes to the user. R15 is used to limit the current through the LED. Capacitor C5 is a bypass capacitor for the microprocessor.

    Microprocessor Pin Functions
    This is a concise list of the function performed by each pin of the microprocessor

    Pin 1
    Audio Input. This is an analog input of the microprocessor which samples the input audio.

    Pin 2
    RAM configuration Input, also RAM2 Chip Select. At power up this line is an input, used to indicate the RAM configuration. High=2 RAM chips, Low=1 RAM chip. If two chips are used, this line is then switched to an output which used as the chip select line by the microprocessor to initiate SPI communication with the second RAM

    Pin 3
    Mode Setting. This is a digital input used to determine if the program will enter normal mode or the test mode. The line is read after power up, and the code runs the mode that is selected. High=normal mode, Low=test mode.

    Pin 4
    Sample Rate Selection. This is a digital input used to determine whether the sample rate should be 11025 Hz or 8000 Hz. High=, Low=. This setting only has an effect during normal operating mode, and it can be changed at any time during operation.

    Pin 5
    GND (VSS)

    Pin 6
    Chip select for DAC. This line is an output which is brought low by the microprocessor to initiate SPI communication with the DAC.

    Pin 7
    Serial Data Input. Data input to microprocessor. This line is the data input from the other SPI devices to the microprocessor.

    Pin 8
    Serial Data Out. Data output from microprocessor). This line is the data output from the
    microprocessor to the other devices on the SPI bus.

    Pin 9
    Chip select for RAM1. This line is an output which is brought low by the microprocessor to initiate SPI communication with the first RAM

    Pin 10
    SCLK . Clock for SPI communications. This line is the clock used by the SPI devices. It is generated by the microprocessor and controls the clocking of data into and out of devices on the SPI bus.

    Pin 11
    Delay Range Select Input A (least significant bit)

    Pin 12
    Delay Range Select Input B

    Pin 13
    Delay Range Select Input C (most significant bit)

    Pin 14
    VCC (+3.3V power for microprocessor)

    Pin 15
    LED indicator output. The LED is used as an indicator during test mode.

    Pin 16
    Oscillator Input. An external 20MHz oscillator is used to drive this pin.

    Pin 17

    Pin 18
    Delay setting Input. This is an analog input of the microprocessor which reads the delay setting

    Step 5: SPI RAM

    Audio Delay Module
    The sampled audio is stored in one or two RAM chips. These are U3 and U2 on the schematic.
    The RAM used here communicates with the microprocessor using the SPI interface. Capacitors C7 and C8 are
    bypass capacitors for the two chips.

    This design stores the waveform samples as 8 bit values. As such, it doesn’t provide extremely high
    fidelity audio, but it is better than AM radio quality. This circuit was designed to use Microchips’ 23K256
    RAM chips, which are 32k bytes in size. (32k by 8). Refer to the datasheet for the part for more details
    about its operation.

    The RAM is used as a large circular buffer. The maximum amount of delay possible depends on the size
    of the buffer and the rate at which the input signal is sampled. The program loops constantly, storing
    new samples into the RAM with each loop. When the number of samples exceeds the RAM size, it
    wraps over and overwrites the oldest samples.

    The system can use either one or two RAM chips, depending on how much capacity is needed. If two
    RAMs are used, then the pull up resistor R13 must be used on the chip select line. This line is sampled
    by the microprocessor at startup, and if it is pulled high, the program will be configured for two RAMs.
    The program will then automatically adjust the way the addressing is handled, so that the two RAMs are
    treated in the software as one large buffer. The CS input of the second RAM MUST be pulled high
    through a resistor, NOT connected directly to VDD. If it is connected directly to VDD, it will short VDD to
    ground when pulling the chip select line low and the processor may likely be damaged. When only one
    RAM is used, the line should be pulled low, also through a resistor instead of directly to ground.

    As mentioned earlier, the maximum delay depends on the buffer size and the sampling rate. Each
    sample is one byte. The maximum amount of audio, in seconds, that can be stored is then given by:
    Max Delay (in seconds) = Buffer size (in bytes) / Sample Rate (in samples per second)

    So, if one 32k byte RAM chip is used, and the sample rate is 11025 samples per second, the maximum
    delay that can be produced is:

    Max Delay=32768 / 11025 = 2.972 seconds

    If the sample rate is 8000 samples per second the maximum delay is:

    Max Delay =32768 / 8000 = 4.096 seconds

    If two RAM chips are used, the max delay times would be 5.944 seconds and 8.192 seconds, respectively
    for the 11025 and 8000 samples per second rates.

    Step 6: SPI DAC

    Audio Delay Module
    The DAC(U4 in the schematic) receives the samples to output from the microprocessor in digital format,
    and converts them to an analog value. It is a SPI device, and shares the data in, data out, and clock lines
    with the SPI RAM.

    The DAC used here a Microchip MCP4921. This DAC is actually a 12 bit device, but only 8 bits of
    resolution are used. The four least significant bits of the values sent to the DAC will always be 0.

    Refer to the datasheet for the part for more details about its operation.

    Capacitor C9 is a bypass capacitor for the DAC.

    Step 7: Reconstruction Filter

    Audio Delay Module
    Audio Delay Module
    Audio Delay Module
    Audio Delay Module
    The reconstruction filter is a low pass filter used to remove the unwanted frequencies that result from the D/A conversion process. The unfiltered output of the DAC will have a staircase shape. The filter removes unwanted higher frequencies that are an inherent part of a sampled data system, so that the result is a smoother waveform that closely resembles the original input. These unwanted frequencies appear as pairs of "images" of the original signal spectrum, and are centered on multiples (harmonics) of the sampling frequency. The image frequencies are like the upper and lower sidebands present in the spectrum of an amplitude modulated (AM) signal. They diminish in amplitude as the frequency increases. The first set of images located around the sampling frequency can still be of significant amplitude, so a low pass filter is used to attenuate them.

    The filter used here is made up of two second order Salen-Key filters cascaded. Op amps U5-B and U5-a are the op amps, configured for an overall cutoff frequency of approximately 6 kHz. R18, R19, C15, and C16 set the cutoff frequency of the first filter section, and R20, R21, C17, and C18 set the cutoff frequency of the second filter section.

    It is not really necessary to use a four pole filter. I designed a four pole filter in and left it in place. The first section can be used alone, with good results.

    The graphs show how the input signal, raw DAC output, and filtered (reconstructed) outputs compare. The first graph shows the response when the input is a sine wave, and the second graph shows the response for an voice signal. Note the staircase shape of the raw DAQ output, and that this is largely removed by the reconstruction filter.

    I’ve also include a graph showing the frequency domain representations of the case where the input is a voice signal. Note that the unfiltered DAC output contains images of the baseband voice signal around the sampling frequency (in this case, 11025 Hz). Also note that the spectrum of the signal output from the reconstruction filter has these image spectra filtered out, and closely resembles the spectrum of the input signal.

    Step 8: Power Supply

    Audio Delay Module
    The power supply uses a 5V regulator VR1 followed by a 3.3V regulator VR2. A diode, D1, on the input to regulator VR1 protects against damage that would be caused if the input power polarity were reversed.

    Capacitors C10, C11, C12, C13, C14 and C15 are used for filtering on the inputs and outputs of the two regulators.

    The 5V power is used only for the 20MHz oscillator and the optional output power amp. All the remaining circuitry (microprocessor, RAM, DAC, and op amps) are powered from 3.3V

    Step 9: Optional Power Amplifier

    Audio Delay Module
    The output of the reconstruction filter is already of suitable amplitude, but it doesn’t have the output required to directly drive a speaker. If the output from the reconstruction filter is to be applied to some other device such as the audio input of a stereo, etc, then the power amplifier descrived here will not be necessary. An alternative to using the power amplifier described here is to use amplified speakers.

    The power amp is based on a LM386 audio amp (U7). The LM386 amp has a fixed gain of 20 as shown. C24 couples the output of the reconstruction filter to the power amp circuit, with resistor R25 and potentiometer R23 used to attenuate the input to the LM386 amplifier. The output of the reconstruction filter can already swing from 0 to +3.3V, so the output from the filter needs be be attenuated before it is input to the LM386 to prevent clipping or distortion.

    C23 was included on the input of the LM386, to filter out interference from AM radio. Without it, the circuit was picking up a local AM station!

    Capacitor C22 is used to couple the output of the LM386 to a speaker. R22 and C21 are used on the output of the 386 to prevent oscillation.

    Note that U7 is powered from +5 volts. C19 and C20 are bypass capacitors on the power inputs to U7.

    Step 10: Software

    The software was written in assembler. Both the source code *.asm file and the *.hex file for
    programming have been included here. The PDF file contains a high level flowchart of how the software

    The software can run one of two modes: Normal Mode, and Test Mode.

    Normal Mode:

    In Normal mode, the software performs the primary function of playing back delayed audio. The attached PDF contains a flowchart showing the steps in the process.

    In this mode the amount of delay is set by the range select switches and the voltage on the delay input. The sampling rate is determined by the sampling rate switch, allowing for either 8000Hz or 11025Hz sampling rates.

    Special Test Mode:

    Special Test Mode is a mode I included to help in verifying proper circuit performance after
    construction. If this mode is selected, the following will happen after power up:

    RAM Tests

    The microprocessor tests the RAM by writing a value to it, and then trying to read it back. If the value
    returned is a match, the test passes, and the LED will turn on for two seconds. If the value does not
    match, then the LED blinks three times. If the circuit has both RAMs populated, the second RAM will be
    tested as well, in the same manner, with the LED turning on for 2 seconds for a pass or blinking three
    times for a fail.

    DAC Test

    The first part of the DAC test sends a value to the DAC so the proper output can be verified. First the
    DAC will output 1/3 of full scale, and hold it for 3 seconds. It will then jump to 2/3 of full, scale, and hold
    for 3 seconds, and then it will jump to full scale and hold for 3 seconds.

    The next part of the DAC test the program will output a 1 kHz sine wave, swinging above and below the
    ½ VDD reference line. So, you should see a sine wave with an amplitude of abut 1.65V, swinging above
    and below 1.65V. The sine wave output is on for 0.25 seconds, and then off for 0.25 seconds, and
    repeats that way indefinitely.

    Audio Delay Module
    Main Audio Delay Program Loop.pdf3 KB
    Audio Delay Module
    Audio Delay Module
    16F88_AUDIO_DELAY.txt36 KB

    Step 11: Construction

    Audio Delay Module

    I constructed the circuit on a solderless breadboard. It just fit on one of the 840 point boards.

    For an enclosure, I used a storage container I picked up at an office supply store. This particular style of box has cover held on by latches on each end. This makes opening the case for changes and adjustments very easy.

    The breadboard fit well within the box, leaving just enough room for mounting switches and potentiometers. The input jacks for power, audio input, audio output, and delay setting are mounted to the sides and ends of the box. The potentiometers for delay setting and output amplifier volume are mounted on the front side. I mounted the gain select switch and the sample rate selection switches inside the enclosure.The picture shows the breadboard in the box, with the inputs and outputs labeled.

    The delay range setting switches are part of a DIP switch mounted on the breadboard.

    Step 12: Conclusion

    Audio Delay Module

    The graph here (same as in Step 7) shows the signal input, DAC output, and reconstruction filter output. For frequencies less than half the sample rate, the circuit performs well at reconstructing the original signal.

    As mentioned in the introduction, there are many possible uses for this circuit. If you can think of more, or have any questions, please comment.



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